Recent years have seen liquid crystal display devices which, as one type of flat display apparatus for use in portable terminal equipment, such as PDA's and mobile phones, have LCD panel driving circuits formed integrally with a glass substrate serving as an insulating substrate constituting part of the LCD panel.
The above type of liquid crystal display device has come to adopt a method for generating driving signals by converting video data from a digital to an analog format through the selection of a plurality of reference voltages in keeping with the video data in question, as disclosed illustratively in Japanese Published Unexamined Patent Application No. 2000-242209.
FIG. 1 is a connection diagram showing a digital-to-analog converter operating through the use of the above method. The digital-to-analog converter 1 includes a plurality of series circuits corresponding to the number of gradations involved, each of the series circuits being composed of switching circuits that are turned on and off depending on the logical values of bits b0 through b4 constituting video data D1. One end of these series circuits is supplied with reference voltages V0 through V31, and the other end of the series circuits is connected to a column line SIGOUT of a liquid display panel. What is shown in FIG. 1 is a setup where the video data D1 occurs in five bits, where the switching circuits are each made of a conductive MOS (Metal Oxide Semiconductor) transistor, and where N and P channels are disposed suitably to select a corresponding reference voltage depending on the values of the video data D1. The digital-to-analog converter 1 is thus arranged to select and output the reference voltages V0 through V31 in accordance with the video data D1.
With the digital-to-analog converter 1 structured as outlined above, this type of liquid crystal display device causes the bits b0 through b4 of the video data D1 to be level-shifted for input to the converter 1. The level-shift arrangement is designed to turn on and off unfailingly the conductive MOS transistors that make up the switching circuits in the digital-to-analog converter.
FIG. 2 is a connection diagram showing a processing block for handling one bit of the video data D1 that is input to the digital-to-analog converter 1. This type of liquid crystal display device has as many one-bit processing blocks as the number of bits constituting the video data D1. The one-bit processing block combines with the digital-to-analog converter 1 of FIG. 1 to form a structure that establishes the gradation of a single liquid crystal cell. A plurality of such structures are furnished to address the liquid crystal cells that are disposed in a horizontally continuous fashion, whereby a horizontal driving circuit is formed.
The one-bit processing block is constituted by a sampling latch 3 and a second latch 4. The sampling latch 3 samples in a suitably timed manner the video data “DATA” input in the raster scan sequence. The second latch 4 serves to latch the latched result from the sampling latch 3 at horizontal scanning intervals before the result is level-shifted.
The sampling latch 3 has CMOS inverters 5 and 6 connected in parallel between a power supply VDD1 and ground. The CMOS inverter 5 is made of an N-channel MOS (called NMOS) transistor Q1 and a P-channel MOS (called PMOS) transistor Q2 with their gates and drains connected in common. Likewise, the CMOS inverter 6 is constituted by an NMOS transistor Q3 and a PMOS transistor Q4 with their gates and drains connected in common. In the sampling latch 3, the output of the CMOS inverter 5 is input to the CMOS inverter 6. The output of the CMOS inverter 6 is input to the CMOS inverter 5 through the NMOS transistor Q5 that is turned on and off by an inverted signal of a sampling pulse “sp.” This setup in the sampling latch 3 constitutes a CMOS latch cell 7 of a comparator structure. In the sampling latch 3, one-bit video data “DATA” is input to the CMOS inverter 5 through the NMOS transistor Q6 that is turned on and off by the sampling pulse “sp.” The data “DATA” has its signal level changed approximately between 0 and 3 V depending on the logical value.
In the sampling latch 3, the latched result from the CMOS latch cell 7 of the comparator structure is input to a CMOS inverter 8 made up of a NMOS transistor Q7 and a PMOS transistor Q8. From the CMOS inverter 8, the result is forwarded to the second latch 4. An inverted output of the CMOS inverter 8 is output to the second latch 4 through a CMOS inverter 9 formed by an NMOS transistor Q9 and a PMOS transistor Q10. The sampling latch 3, as shown in FIGS. 3A through 3F, thus latches the data “DATA” (FIG. 3A) in keeping with the sampling pulse “sp” (FIG. 3B) and outputs the latched result 1Lout (FIG. 3C).
In the second latch 4, CMOS inverters 10 and 11 constitute a CMOS latch cell 12 of a comparator structure. The CMOS inverter 10 is made up of an NMOS transistor Q11 and a PMOS transistor Q12, and the CMOS inverter 11 is composed of an NMOS transistor Q13 and a PMOS transistor Q14. The latched result 1Lout from the sampling latch 3 and an inverted output of the latched result 1Lout are input to the CMOS latch cell 12 through NMOS transistors Q15 and Q16 activated by a latch pulse “oe1.”
In the second latch 4, the CMOS latch cell 12 is connected to a ground VSS1 and a negative power supply VSS2 through NMOS transistors Q17 and Q19 that are turned on and off complementarily by an inverted signal “xoe2” of the pulse “oe2.” Likewise the CMOS latch cell 12 is connected to power supplies VDD2 and VDD1 through PMOS transistors Q20 and Q22. The second latch 4 feeds the output of the CMOS latch cell 12 to the corresponding bit of the digital-to-analog converter 1 through a CMOS inverter 13 made up of an NMOS transistor Q23 and a PMOS transistor Q24. In the second latch 4, the pulse “oe2” (FIG. 3E) is provided so as to set the CMOS latch cell 12 (at time t1) to the same power supply VDD1 that is used by the sampling latch 3. Thereafter, the latched result from the sampling latch 3 is latched (at time t2) by the CMOS latch cell 12 in accordance with the latch pulse “oe1” (FIG. 3D). With the latched result thus latched by the CMOS latch cell 12, the sampling latch 3 is disconnected (at time t3) on a trailing edge of the latch pulse “oe1.” Then the power supply voltage for the CMOS latch cell 12 is switched (at time t4) on a trailing edge of the pulse “oe2,” whereby the latched result is level-shifted for output (FIG. 3F).
In the second latch 4 described above with reference to FIG. 2, the transistors Q20 and Q22, which should act complementarily to switch the power supplies for the CMOS latch cell 12, cannot be entirely prevented from going on simultaneously. The instantaneously concurrent activation of the two transistors incurs a large amount of momentary power dissipation. More specifically, flow-through currents can take place from the power supply VDD2 to the power supply VDD1 or from the power supply VSS1 to the power supply VSS2.
If such momentary flow-currents are prevented, this will reduce power dissipation of the above type of flat display apparatus and contribute to improving its ease of use.
If the structure of the second latch 4 is made simpler, this will provide the above type of display apparatus with a narrower display framework than before.